The PCI (Peripheral Component Interconnect) Local Bus is a high performance, 32-bit or 64-bit bus with multiplexed address and data lines. The intended use of the bus is as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The PCI architecture supports many complex features, including I/O expansion through PCI-to-PCI bridges, peer-to-peer (device-to-device) data transfers between sending devices (masters) and receiving devices (targets), as well as, multi-function devices and both integrated and plug-in devices. A "transaction" on the PCI bus generally refers to the exchange of data between PCI bus devices, categorically called "agents". A "master" is the agent requesting control of the bus for initiating a transaction. A "target" is the selected agent which completes the transaction. Each master has a separate bus access request and bus grant signal. Details of the PCI bus architecture are defined in the PCI Local Bus Specification, Revision 2.1, available from PCI Special Interest Group, Oregon, which is incorporated herein by reference.
The PCI definition currently supports transactions at a frequency up to 66 megaHertz (MHz). The PCI architecture utilizes a separate non-bused clock line to each PCI device on the bus for clocking control, address, and data signals of each transaction in a synchronous fashion. With the use of separate non-bused clock lines to each PCI device, the following timing budget requirements result, as represented by the timing diagram illustrated in FIG. 1. Accordingly, as is seen the total cycle-time for a transaction (Tcyc) is represented by the following equation: EQU Tcyc.ltoreq.T.sub.val +T.sub.prop +Tskew+Tsu
where: T valid (Tval) is the allocated time for a device to place valid data on the bus relative to the appropriate clock edge of the clock signal in the device. T setup (Tsu) is the time allocated for a device to clock data off the bus from the appropriate clock edge of the clock signal in the device. T propagation (Tprop) is the propagation time of the signals across the bus. T skew (Tskew) is the clock skew between the clock signals present in the devices for the sender and receiver of data on the bus.
For the current PCI definition, Tval is 6 ns (nanoseconds), Tsu is 3 ns, Tskew is 1 ns, and Tprop is 5 ns, providing a total cycle time of 15 ns, and a resultant frequency of 66 MHz. The timing budget that establishes the cycle time for transactions tightens as the frequency gets higher, since the total cycle time Tcycle becomes smaller. While 66 MHz has conventionally been a fast enough operating frequency, advancements in device technology create opportunities to operate at even higher operating frequencies. Unfortunately, the current definition and timing characteristics for the PCI architecture limit the highest frequency that is achievable to 66 Mhz.
Accordingly, a need exists for a system and method for allowing transactions to be performed at higher frequencies on a PCI bus architecture. The system and method should be compatible with existing architectures, should be easy to implement and cost effective. The present invention addresses such a need.